Memory Speed:  The link between the CPU and memory is called the memory bus. Often, it runs at the same speed as the Front Side Bus (FSB), which regulates the communication between the CPU and lots of other system components. The newer Intel Pentium Processors seem to run better with the memory using an asynchrous 4:5 memory divider, meaning that the memory is running faster than the front side bus. The bus speeds are measured in MHz, or million clock cycles (CC's) per second.

Modern processors transmit 8 bits of data on every clock cycle, and all Athlon 64 and the older Socket 478 Pentium 4 CPUs run with a 200MHz memory bus. Newer Intel Pentium CPUs that use the LGA775 socket use either a 266MHz or 333MHz memory bus speed. The memory bus speed depends on whether they're an Extreme Edition or not - standard Pentium CPUs use a 266MHz memory bus, while Extreme Editions use a 333MHz bus.

If you multiply 400 (200 times 2 as Double Data Rate (DDR) memory runs at twice the clock speed) by 8, and you get a theoretical maximum figure of 3200Mbits/s transfer - hence the memory rating speed PC3200 found on the label of most new sticks of DDR memory. With the newer Pentium CPUs, you will see modules labelled with PC2-4200 (DDR2-533), PC2-5400 (DDR2-667) and modules up to PC2-8000 (DDR2-1000).

Memory Latency:  Addressing memory is much like reading from a large, multiple page spreadsheet. It doesn't matter how quickly you can read, before you can start you have to find the page the data you want is on (this is known as tRAS), work your way to the row and column the data's stored on (tRCD), when you've found the cell you want it takes some time before you start reading (CAS) and when you get to the end of a row you have to switch to the next, which takes time (tRP).

tRAS is the time required between the bank active command and the precharge command. Or in simpler terms, how long the module must wait before the next memory access can start. It doesn't have a great impact on performance, but it can impact system stability if set incorrectly. The optimal setting ultimately depends on your platform - the best thing to do is to run Memtest86 on your system with variable tRAS settings to find the fastest setting for your system.

The tRCD timing relates to the number of clock cycles taken between the issuing of the active command and the read/write command. In this time, the internal row signal settles enough for the charge sensor to amplify it. The lower this is set, the better - the optimal setting is either 2 or 3, depending on how capable your memory is. As with any other memory timing, setting this too low for your memory can cause in system instabilities.

CAS Latency is the delay, in clock cycles, between sending a READ command and the moment the first piece of data is available on the outputs. Setting CAS to 2.0 seems to be the holy grail with memory manufacturers, but the difference between tight timings and high memory bus speeds is an arguement that we hope to settle over the course of this article.

The tRP timing is the number of clock cycles taken between the issuing of a precharge command and the active command. It could also be described as the delay required between deactivating the current row and selecting the next row. In conjunction with the tRCD timing, which relates to the time taken between the issuing of the active command and the read/write command, the time required to switch banks (or rows) and then select the next cell for reading/writing or refreshing is a combination of the two timings.
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