There are delays between each of the steps in memory access. These delays are referred to as latencies and expressed as a number of clock cycles. Here's a brief explanation of some of the most common, and important, memory timing parameters that affect access latencies:
When we see what a RAM’s CAS latency is, it is 4 numbers, such as 2-2-2-5, which correspond with CAS – tRCD – tRP – tRAS. You should be able to change the CAS Latency in your BIOS. In most BIOSes, it can be found under the “advanced chipset” menu, though it can be found in different areas in different BIOSes.
CAS stands for Column Address Strobe. This is the number of memory cycles that pass between the time a column is requested from the active page and the time the data is ready to send across the bus. This number is usually 2, 2.5, and 3, on DDR memory. This is actually the last part to come into effect.
RAS to CAS Delay is referred to as tRCD. This is the delay in memory cycles between the time a row is activated and when data within the row can be requested. This only happens when data is not on the active row.
tRP is the time for RAS Precharge. This is the time in memory cycles that is required to clear out the active row out of the cache, before a new row can be requested. In other words, it’s the time it takes for the memory to stop accessing one row and start accessing another. Once again this only takes place it the data is not in the active row.
tRAS refers to the minimum time that a row must remain active before a new row can be activated in each memory bank. A new row can not be opened until the minimum amount of time has passed. If there is more than one bank on memory, this will help the performance of the tRAS. If there is only one active bank, then the need to change rows is guaranteed, and if there is more than one bank with memory, then there is only half the chance that there will be a need to change rows. In turn, the tRAS will only come into effect half the time. The tRP and tRAS together are often referred to as the Row Cycle time, because they happen together.
No discussion of memory latency would be complete without mentioning the DRAM command rate. The command rate is the delay between when a memory chip is selected and when the first active command can be issued. The factors that determine whether a memory subsystem can tolerate a 1T command rate are many, including the number of memory banks, the number of DIMMs present, and the quality of the DIMMs. Some memory manufacturers claim that their DIMMs are rated for operation with a one-cycle (1T) command rate.
Since latencies refer to delays, lower is better. That doesn't mean you should hop into your motherboard's BIOS and set each memory timing option to its lowest possible value, though. Memory modules are rated for a specific set of latencies at a given clock speed, and they're generally not stable with lower latencies. A DIMM's latencies are usually expressed as a series of four hyphenated numbers corresponding to the CAS latency, RAS-to-CAS delay, RAS precharge, and active-to-precharge delay. Low latency DDR400, for example, is generally rated for 2-2-2-5 timings at 400MHz. That refers to two cycles of CAS latency, RAS-to-CAS delay, and RAS precharge, and five cycles of active-to-precharge delay.
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